Currently intellectual property (IP) cores (or blocks) are validated against all base platform/structured application specific integrated circuits (ASICs). When a new platform/structured ASIC becomes available, a new validation is performed for all the IP (i.e., the cores have to be hand-placed and the timing of the cores has to be checked). Hand-placing and checking timing are time consuming, tedious and prone to error.
Increasingly, valid placement and timing closure of key IP is becoming a problem for platform/structured ASIC customers. A mechanism to manage the valid placements of IP on any given platform/structured ASIC can be key to ensuring the scalability of a product line. Defining a mechanism for allowing valid placement of firm and hard IP cores may significantly improve the turn around time for designs that use such IP.